1. Field of the Invention
The present invention relates to a semiconductor device with a multiport RAM macro accessible from plural ports, particularly relates to a semiconductor device including a test circuit for setting a test condition for the RAM macro.
2. Description of Related Art
A multiport RAM macro accessible from plural ports can be accessed to a memory cell independently and asynchronously from respective ports. There is also a case in which while carrying out an operation of reading data from a certain port for the memory cell, an access is made from other port to the same memory cell. Hereinafter, this is referred to as a simultaneous access operation from the plural ports to the same memory cell.
An explanation will be given of the simultaneous access operation to the same memory cell in a dual port RAM. FIG. 7 is a memory cell circuit diagram of a dual port RAM. A memory cell M1 of a dual port RAM is constituted by two driver transistors of MN1 and MN2, and load driver transistors of MP1 and MP2. Further, transistor MN3, MN4, MN5 and MN6 are access transistors for switching accesses from the respective ports to the memory cell M1.
An explanation will be given of the simultaneous access operation to the same memory cell from A port and B port when the memory cell M1 holds “0” data (NODE1 is at “L” level, NODE2 is at “H” level) in such a dual port RAM.
In a read operation from A port, a word line WLA becomes an active level and the access transistors MN3 and MN4 are turned ON. When NODE2 is at “H” level, the driver transistor MN2 is turned ON, and a charge of a bit line DTA precharged to a power supply voltage is drawn along a broken line. At this occasion, when the memory cell M1 is accessed through B port, a word line WLB of B port becomes an active level, and the access transistors MN5 and MN6 of B port are turned ON. Although a charge of a precharged bit line DTB is drawn similar to the charge of the bit line DTA, by being MN3 and MN5 turned ON simultaneously, in comparison with the case of being either one of MN3 and MN5 turned ON, a potential level of NODE1 is elevated. By elevating the potential level of NODE1, drain-source voltages Vds of the access transistors MN3 and MN5 are lowered, as a result, a speed of drawing the charge of the bit line DTA is retarded. Therefore, a sufficient read time period cannot be ensured within a set cycle and data reading becomes uncertain.
On the other hand, JP-A-2006-134379 describes a method of firmly carrying out data-read operation even in the above-described case of selecting the same row address at the same cycle. FIG. 9 shows a dual port RAM described in JP-A-2006-134379. According to the dual port RAM, when the same row address is selected by accesses from plural ports, a control signal RP outputted by a read control circuit 116a of one port for memory access is transmitted also to a write control circuit 106a of other port, and a delay is produced in controlling other port such that an access transistor for the port is not activated simultaneously. JP-A-2006-134379 describes a method of controlling timings of outputting activating signals of ports different from each other in this way.
However, a write operation is retarded until data is read firmly in a read operation by controlling timings of outputting the activating signals of the different ports, and therefore a cycle time is deteriorated.
When the above-described control of timings of outputting the activating signals is not carried out in order to avoid deterioration in the cycle time, it is made necessary to set the power supply voltage to be high in order to normally operate the RAM macro even in the simultaneous access operation from the plural ports to the same memory cells.
The power supply voltage necessary when the simultaneous access operation is carried out is provided with a characteristic as shown by FIG. 8 for an access delay difference between ports. In FIG. 8, the abscissa designates an access delay difference between the ports, the ordinate designates a power supply voltage necessary for a normal operation. Here, a delay value 0 indicates that a time period of making an access from A port and a time period of making an access from B port are quite the same, a left side of the delay value 0 indicates a case in which an access of B port precedes an access of A port, and a right side of the delay value 0 indicates a case in which an access of B port is delayed from the access of A port. As shown by FIG. 8, it is known that the highest power supply voltage is needed when the time periods of making accesses from A port and B port are the same.
Therefore, in order to guarantee such a power supply voltage, a situation in which time periods of making accesses from plural ports are quite the same needs to be reproduced in testing the multiport RAM macro. However, clock signals supplied to the respective ports are provided with a delay difference among the signals and it is difficult to operate the clock signals supplied to the respective ports completely simultaneously. Further, word lines of the respective ports are activated in accordance with such clock signals, and therefore, time periods of bringing word lines of the plural ports at active levels cannot be made to coincide with each other. Further, it is also difficult to set such that the time periods of bringing the word lines of the plural ports at the active levels are overlapped the most.
A power source standard in testing can also be corrected based on the characteristic of the power supply voltage as shown by FIG. 8. For example, as shown by FIG. 8, assuming that a difference of a delay between respective ports is a, by setting the power supply voltage to be high by b, a power supply voltage standard under the worst condition can be set. When a skew between ports is c′, a voltage to be corrected inherently is to be small since measurement is carried out at a vicinity of the worst condition. However, an actual delay amount is unknown in testing, and therefore, when a power supply voltage standard higher by an amount b′, is set by assuming the delay amount as a delay amount a′, an excessive power supply volgate is guaranteed.